Manifold is a parallel discrete event simulation (PDES) framework designed for the simulation of modern multicore computer architectures. The framework is composed of two layers: a simulation kernel layer and a model layer. The simulation kernel layer contains a PDES simulation kernel that is responsible for processing events and communicating with other processes to ensure simulation correctness. The model layer contains computer architecture models. The model layer is component-based with defined interfaces between components to facilitate the integration of third party tools. The layered design allows users to easily integrate their own models and build parallel simulators.
Manifold is distributed as a source package, which contains:
- The simulation kernel.
- Timing models for all major components of a multicore processor
- A few simulation programs that can be readily used and/or serve as examples.
Major features of Manifold include the following:
- Support for both sequential and parallel simulations. The current release supports serial simulation. The parallel simulator is under test release end of summer.
- Simulation kernel support for three time bases: ticked (integer) time, floating-point time, and mixed time.
- The QSim multicore emulator front-end
- The Energy Introspector (EI) power, energy, thermal, and reliability modeling library for integration with multicore processor models.
Manifold is an open-source project released under the New BSD license. The source code package is available at this download link.
Manifold adopts a layered software architecture, which is composed of two layers: a simulation kernel layer, and a models layer, as shown in the following figure.
The kernel layer contains all the PDES functionalities, including event management, event processing, and inter-process communication. This layer is responsible for ensuring simulation correctness as expected from a PDES system.
The models layer contains computer architecture models provided by Manifold, and any user-designed models that can be integrated with the kernel layer. Models are constructed as Manifold components that communicate via Manifold links.
The cross-model layer contains functionalities that depends on multiple components in the models layer.
The simulator layer is where the simulator programs are created. The simulators use one or more lower layers.
The layered architecture has two major benefits. First, the kernel layer hides all the details about PDES, thus allowing a parallel simulation program to be built with minimal knowledge of PDES. Secondly, using the kernel’s small, well-defined interface, the users can easily integrate their own computer architecture models and build parallel simulation programs. This is envisioned as the most prevalent use of Manifold.
Furthermore, as the above diagram shows, the major components in the models layer have no inter-dependence. Manifold defines a set of standard interfaces between major components, such as the processor-cache interface. This makes components of the same type interchangeable, removes dependence between models, and allows modelers to easily mix-and-match components when building their simulation programs.
Functionalities of the simulation kernel can be divided into two categories:
- PDES functionalities.
- Services for the upper layer.
Since computer architecture simulation usually involves periodic events such as those triggered by a clock, the Manifold kernel is a mixture of an asynchronous discrete event simulation system and a time-stepped simulation system. The kernel supports three time-bases: integer time called ticked time for clock-triggered events, floating-point time for arbitrary asynchro0nous discrete events, and the mixture of the two.
As in any discrete event simulation system, the kernel maintains data structures for event management, ensuring events are processed in the correct order.
As a PDES system, the kernel has the additional responsibility of synchronizing with other processes to ensure simulation correctness of the entire system. The kernel currently supports two conservative synchronization protocols: lower bound time stamp (LBTS) and Null-message. We are in the process of adding optimizations to improve the scalability of these two implementations in the context of many core processor simulation.
In addition to the PDES functionalities, which are hidden from the upper layer, the kernel also provides other simulation services. One of the most services is a function that allows a model to propagate an output change. In fact, the dependency of the models layer on the kernel layer is to a great extent due to the use of this service. Other services include setting up component interconnections, start and stop of simulation, and so on, which are more likely used by the simulation programs than the models in the models layer.
Manifold repository currently provides the following models.
- Zesto: an OOO and in-order core model.
- MCP-cache: a coherent cache model.
- Iris: a flit-level interconnection network model.
- CaffDRAM: a DRAM and memory controller model
- QSim: A multicore emulator based on QEMU to be used as a front-end for Manifold timing models.
We anticipate addition of many more models into the Manifold repository. Simulators can be built with different combinations of models. We welcome contributions from interested parties who wish to contribute point tools and models. A brief description of the current set of models is below.
Zesto is a cycle-level x86 processor simulator built on top of SimpleScalar. Its strength is in low-level cycle-by-cycle modeling of a modern, out-of-order core pipeline. Zesto models include both in-order and out-of-order processors. The core models are available as three distinct object classes that correspond to three different front-ends, which respectively accept instruction inputs from three different sources: Pin trace files, QSim library, or Qsim server.
MCP-cache is a coherent cache model based on Manager-Client Pairing (MCP), a methodology for creating coherence hierarchies that allows different coherence realms within the hierarchy to use different protocols. The current distribution includes an implementation of the MESI protocol.
Iris is a cycle level interconnection network model developed for multicore and multi-node systems. Its main components include a network interface model and a pipelined router model along with topology generators.
Major features of Iris include:
- Supports virtual channels.
- Supports for k-ary 2D torus, and ring topologies – Support for other topologies like mesh, fat tree and flattened butterfly are planned for future work.
- Supports request-reply network.
- Supports single-flit packets.
- Supports generic network packet data types. Iris does not define its own network packet. Instead, it supports any user-defined data type that complies with its requirements.
- Supports sequential and parallel simulation modes. In parallel simulation, the network interfaces and routers can be assigned to a single logic process or different logic processes.
CaffDRAM is a timing model for a DRAM controller. It models the memory as a hierarchy consisting of channels, ranks, and banks. For each memory request, the latency is computed based on the current state of the target memory bank.